Numerous output driver circuits have been developed for integrated circuits and systems. In many cases, these driver circuit structures are designed to minimize noise for digital applications where the number of outputs is large, e.g., a 32-bit or 64-bit data bus or address bus. One source of noise in high performance logic circuits is a phenomenon known as “ground bounce”, which typically occurs when a transient current passes through the package inductance, producing a voltage glitch or spike that can cause a logic error. Digital circuits normally produce transient noise when the output switches from one logic level to the complementary logic level. According to fundamental laws of physics, this type of transient noise increases whenever the package inductance increases, the transient time decreases, the capacitive load increases, or the number of drivers increases.
To combat the problem of ground bounce noise, circuit designers have tried a variety of different approaches, which include alteration of the package inductance, and circuit designs constrained to produce the smallest transient current possible. This latter approach to reducing noise involves controlling the transient current waveform of the output driver. An example of this design approach is disclosed in U.S. Pat. No. 4,947,063, which teaches reducing noise in an output driver by utilizing a ramp-shaped current pulse to change the output voltage. By way of further example, U.S. Pat. Nos. 4,947,063; 4,783,601; 5,510,744; 5,517,130; 6,127,746; and 6,329,866 disclose various structures and methods of output drivers exhibiting low noise performance.
The basic problem with past output driver circuit designs is that the magnitude of the ramped current pulse is often difficult to control precisely. This limitation on device performance is often due to variations that exist in manufacturing process parameters and device operating conditions (i.e., supply voltage, temperature, etc.). For instance, many prior art implementations still suffer from problems associated with process variation of resistance values, in which process fluctuations in sheet resistance value lead to significant variations (e.g., 25% to 50%) in current references of the output driver.
Variations across process or operating conditions in the magnitude of the ramped shaped current from an optimal value cause an increase in either the transient noise or transition delay. An increase in transition delay reduces timing margin, causes an increase in the error rate, or requires a reduction in the maximum data rate. Conversely, an increase in the transient noise voltage produces digital errors, which can cause a loss of data, or even produce catastrophic failure by way of latch-up in CMOS circuits. As process variations produce a wider variance in specific process parameters, the performance of the entire digital system thus decreases.
Therefore, what is needed is a new circuit topology and method that minimizes transient noise from digital switching by reducing sensitivity to process parameters.